Semiconductor memory device and method of manufacturing the same

ABSTRACT

In a semiconductor memory device having cylindrical capacitors, word lines and a bit line are formed on a semiconductor substrate. A cylindrical storage node is connected to a conductive layer. The cylindrical storage node is provided at its inner wall with protruded conductive conductors which protrudes in a radially inward direction of the cylindrical storage node. A surface of the cylindrical storage node is covered with a capacitor insulating film. The outer surface of the cylindrical storage node is covered with a cell plate with the capacitor insulating film therebetween.

This application is a continuation of application Ser. No. 08/253,435,filed Jun. 6, 1994, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a semiconductor memorydevice, and in particular, to an improvement of a semiconductor memorydevice in which a sufficient capacitor capacity can be ensured even ifdegree of integration is increased. The present invention also relatesto a method of manufacturing such a semiconductor memory device.

2. Description of the Related Art

In recent years, demands for semiconductor memory devices have beenrapidly increased owing to remarkable spread of information equipmentssuch as computers. In connection with function, such devices have beendemanded that have a large scale storage capacity and can operate at ahigh speed. In compliance with these demands, technologies have beendeveloped for improving degree of integration, response and reliabilityof the semiconductor memory devices.

Dynamic random access memories (DRAMs) have been known as a kind ofsemiconductor memory devices which enable random input and output ofstorage information. In general, the DRAM is formed of a memory cellarray, which is a storage region storing a large number of storageinformation, and a peripheral circuitry required for external input andoutput.

FIG. 1 is a block diagram showing a structure of a conventional DRAM. InFIG. 1, a DRAM 1 includes a memory cell array 2 which stores datasignals of stored in formation, a row and column address buffer 3 whichexternally receives an address signal for selecting a memory cell merelyforming a storage circuit, a row decoder 4 and a column decoder 5 whichdecode the address signal to designate the memory cell, a sense refreshamplifier 6 which amplifies and reads the signal stored in thedesignated memory cell, data-in buffer 7 and a data-out buffer 8 fordata input and output, and a clock generator 9 generating a clocksignal. The memory cell array 2 which occupies a large area on thesemiconductor chip is provided with a plurality of memory cells, whichfunction merely to store the information and are disposed in a matrixform .

FIG. 2 is an equivalent circuit diagram showing memory cells for fourbits forming the memory cell array. Each memory cell in the figure isformed of one MOS transistor and one capacitor connected thereto, andthus is of so-called an one-transistor/one-capacitor type. Since thememory cells of this type have a simple structure, the degree ofintegration of the memory cell array can be increased easily, and theyhave been widely used in DRAMs of a large capacity.

The memory cell of the DRAM can be classified into several types basedon the structure of the capacitor.

FIG. 3 is a cross section of a memory cell having a typical stacked typecapacitor in the prior art. Referring to FIG. 3, the memory cellincludes one transfer gate transistor and one stacked type capacitor.The transfer transistor includes a pair of source/drain regions 11formed at a surface of a silicon substrate 10, and gate electrodes (wordlines) 12 formed on the surface of the silicon substrate 10 with aninsulating layer therebetween. The stacked type capacitor is formed of alower electrode (storage node) 14, which is extended over the gateelectrode 12 and a field isolating film 13, and is connected to one ofthe source/drain regions 11, a dielectric layer 15 formed on the surfaceof the lower electrode 14, and an upper electrode (cell plate) 16 formedon the surface of the dielectric layer 15. The upper electrode 16 iscovered with an interlayer insulating film 19 disposed on the siliconsubstrate 10. In the interlayer insulating film 19, there is provided acontact hole 18 through which the surface of the other source/drainregion of the transfer gate transistor is exposed. A bit line 17 isconnected to the other source/drain region 11 of the transfer gatetransistor through the contact hole 18.

FIG. 4 is a plan showing a semiconductor memory device having acylindrical capacitor, which belongs to another type of DRAM and isdisclosed in Japanese Patent Laying-Open No. 02-89869 (1990). FIG. 5 isa cross section taken along line V--V in FIG. 4.

Referring to these figures, a plurality of word lines 12a, 12b, 12c, 12dand 12e are formed on the surface of the silicon substrate 10. Bit lines21 extend perpendicularly to the word lines 12a, 12b, 12c, 12d and 12e.Memory cells are provided near crossings of the word lines and bitlines.

Each memory cell is formed of one transfer gate transistor 22 and onecapacitor 23. The transfer gate transistor 22 includes a pair ofsource/drain regions 11 formed at the surface of the silicon substrate10, and the gate electrodes (word lines 12a and 12b) formed on thesurface of the silicon substrate 10. The word lines 12a, 12b, 12c and12d are covered with an insulating layer 24 provided on the siliconsubstrate 10. In the insulating layer 24, there is provided a contacthole 25 through which one of the source/drain regions 11 is exposed.

Through the contact hole 25, a storage node 26 is connected to one ofthe source/drain regions 11. The storage node 26 includes a bottomconductive portion 27 and a side wall conductive portion 28. The bottomconductive portion 27 is in contact with one of the source/drain regions11 through the contact hole 25 and extends along the surface of theinsulating layer 24. The side wall conductive portion 28 is continuouswith the outer periphery of the bottom conductive portion 27 and extendsupwardly therefrom.

The surface of the storage node 26 is covered with a capacitorinsulating film 29, and is further covered with a cell plate 30 with thecapacitor insulating film 29 therebetween. The cell plate 30 is coveredwith an interlayer insulating film 31 provided on the silicon substrate10. On the interlayer insulating film 31, there are providedinterconnection layers 32, which are covered with a protection film 33provided on the silicon substrate 10.

In the cylindrical capacitor having the aforementioned structure, sincethe storage node 26 has the side wall conductive portion 28 of whichsurface contributes to the capacitor capacity, the overall capacity ofthe capacitor is large.

A method of manufacturing the semiconductor memory device shown in FIG.5 will be described below.

FIGS. 6-20 are fragmentary cross sections of the semiconductor memorydevice at a series of steps in a process of manufacturing thesemiconductor memory device shown in FIG. 5.

Referring to FIG. 6, a field oxide film 13 is formed on the main surfaceof the silicon substrate 10 by the LOCOS method.

Referring to FIG. 7, a gate insulating film 34 is formed on the surfaceof the silicon substrate 10, and then, the word lines 12a, 12b, 12c and12d made of polysilicon are formed thereon. The insulating layers 24 areformed to cover the word lines 12a, 12b, 12c and 12d. Using the wordlines 12a, 12b, 12c and 12d covered with the insulating layers 24 as amask, impurity ions are implanted into the surface of the siliconsubstrate 10 to form the source/drain regions 11.

Referring to FIG. 8, a layer of metal such as tungsten, molybdenum ortitanium having a high melting point is deposited on the surface of thesilicon substrate 10 for forming the bit line 17, and is patterned intoa predetermined configuration. The layer thus patterned forms the bitline 17 which is in direct contact with one of the source/drain regions11 of the transfer gate transistor. An insulating layer 35 is formed tocover the surface of the bit line 17.

Referring to FIG. 9, a first polysilicon layer 36 containing impurityintroduced thereinto is deposited on the surface of the siliconsubstrate 10 by the CVD method.

Referring to FIG. 10, an insulating layer 37 made of a silicon oxidefilm is deposited on the surface of the silicon substrate 10.

Referring to FIG. 11, resist patterns 38 of a predeterminedconfiguration are formed on the surface of the insulating layer 37. Aswill be seen later, a width w of the resist pattern 38 determines adistance between adjoining capacitors.

Referring to FIG. 12, the insulating layer 37 is selectively etchedusing the resist patterns 38 as a mask.

Referring to FIGS. 12 and 13, the resist patterns 38 are removed, andthen a second polysilicon layer 39 containing impurity introducedthereinto is deposited on the whole surface of the silicon substrate 10by the CVD method so that the second polysilicon layer 39 covers theside walls and upper end surfaces of the patterned insulating layers 37.

Referring to FIG. 14, a resist 40 is applied to the surface of thesilicon substrate 10 so that the resist 40 fully covers the uppermostsurfaces of the second polysilicon layer 39.

Referring to FIGS. 14 and 15, the resist 40 is etched back to expose theupper end surfaces of the second polysilicon layer 39.

Referring to FIGS. 15 and 16, the exposed upper end surfaces of thesecond polysilicon layer 39 are etched. Thereafter, the insulatinglayers 37 are removed by etching, e.g., with HF liquid.

Referring to FIGS. 16 and 17, anisotropic etching is effected to removeexposed portions 36a of the first polysilicon layer 36 in aself-aligning manner. Thereafter, the resist 40 is removed. Throughthese steps, the bottom conductive portion 27 and side wall conductiveportion 28 of the storage node 26 are formed.

Referring to FIG. 18, the capacitor insulating film 29 made of, e.g.,silicon nitride, silicon oxide, tantalum pentaoxide or hafnium oxide isformed on the surface of the storage node 26.

Referring to FIG. 19, the cell plate 30 is formed to cover the outersurface of the storage node 26 with the capacitor insulating film 29therebetween. The cell plate 30 is made of material such as polysiliconcontaining impurity introduced thereinto.

Referring to FIG. 20, the interlayer insulating film 31 is formed on thewhole surface of the silicon substrate 10 to cover the cell plate 30.The interconnection layers 32 having a predetermined configuration areformed on the interlayer insulating film 31. The protection film 33covering the interconnection layers 32 is formed on the whole surface ofthe silicon substrate 10. Through the aforementioned steps, thesemiconductor memory device shown in FIG. 5 is completed.

The semiconductor memory device having the cylindrical capacitors havethe structure described above and is manufactured by the aforementionedmethod.

Meanwhile, such a method was recently proposed that, in order toincrease the capacitor capacity, projections formed of silicon particlesare provided at the surface of the cylindrical storage node so as toincrease the surface area of the capacitor (IEDM, Technical Digest,1992, pp 259-263).

FIG. 21 is a cross section of a semiconductor memory device having acylindrical capacitor which is manufactured by the method proposed inthe above reference.

The prior art shown in FIG. 21 differs from the prior art shown in FIG.20 in that silicon particles 41 are provided on the outer surface of thestorage node 26, the capacitor insulating film 29 is provided on theouter surface of the storage node 26 including the surfaces of thesilicon particles 41, and the cell plate 30 is provided on the capacitorinsulating film 29.

The semiconductor memory device shown in FIG. 21 is obtained only by anideal manufacturing process, and has such a problem that a practicalmanufacturing process cannot produce the silicon particles 41 having auniform diameter shown in the figure.

This problem will be described below with reference to the drawings.

FIG. 22 is a fragmentary cross section of the semiconductor memorydevice at a major step in the process of manufacturing the semiconductormemory device shown in FIG. 21.

The step shown in FIG. 22 is carried out between the steps shown inFIGS. 17 and 18.

The silicon particles 41 are formed on the side wall of the storage node26 in the following manner.

The silicon substrate 10 provided with the storage node 26 is introducedinto a pressure-reduced CVD chamber. A temperature of 600° C. and a highvacuum state of not more than 1×10-7 Torr are maintained in the CVDchamber. Under there conditions, Si₂ H₆ gas or the like is flowedthrough the CVD chamber for ten seconds, so that minute cores of thesilicon particles 41 of nearly hemispheric shapes are formed on thesurfaces of the bottom conductive portion 27 and side wall conductiveportion 28 of the storage node 26.

Referring to FIG. 22, the silicon particle generally has a size of 500to 1000 Å. However, if the surface state of the storage node 26 isuneven or the process condition is not uniform, the density and sizes ofthe silicon particles 41 fluctuate.

The uneven surface state of the storage node 26 may be caused, forexample, if amorphous silicon at the surface of the storage node 26 ispartially crystallized, if residue of resist and/or etching residue arepresent on the surface of the storage node, and if a natural oxide filmis formed on the surface of the storage node. The nonuniform processcondition may be caused, for example, by variation of the temperatureand/or reduction of the vacuum in the CVD process.

If the sizes of the silicon particles 41 are uneven, a following problemis caused if a space between adjoining storage nodes is small inaccordance with high density and high degree of integration of elements.

Referring to FIG. 23, the adjoining storage nodes 26, which are spacedby a short distance from each other, may be short-circuited via thesilicon particles 41, resulting in bit error.

Even in the case where the short-circuit does not occur, the spacebetween the adjoining storage nodes 26 is reduced by a distancecorresponding to the thicknesses of the huge silicon particles 41, sothat the capacitor insulating film 29 and cell plate 30 may notcompletely cover the outer surfaces of the storage nodes 26. Thisresults in reduction of the memory cell characteristics.

SUMMARY OF THE INVENTION

The present invention has been developed to overcome the above problems,and has an object to obtain a semiconductor memory device of a largecapacitor capacity.

Another object of the invention is to provide a semiconductor memorydevice having cylindrical capacitors and capable of preventingshort-circuit between adjoining storage nodes.

Still another object of the invention is to provide a method ofmanufacturing a semiconductor memory device having such cylindricalcapacitors.

According to an aspect of the invention, a semiconductor memory deviceincludes a semiconductor substrate which is provided at its main surfacewith a conductive layer. A word line and a bit line are formed on thesemiconductor substrate. The word line and the bit line are covered withan insulating film formed on the semiconductor substrate. The insulatingfilm is provided with a contact hole for partially exposing theconductive layer. A cylindrical storage node is electrically connectedto the conductive layer. The cylindrical storage node includes a bottomconductive portion which is in contact with the conductive layer throughthe contact hole and is disposed along a surface of the insulating film,and a side wall conductive portion which is continuous with and extendsupwardly from an outer periphery of the bottom conductive portion. Thecylindrical storage node formed of the bottom conductive portion and theside wall conductive portion has an inner wall provided with a protrudedconductor which protrudes in a radially inward direction of thecylindrical storage node. The semiconductor memory device furtherincludes a capacitor insulating film which covers a whole outer surfaceof the cylindrical storage node including an outer surface of theprotruded conductor. There is also provided a cell plate covering theouter surface of the cylindrical storage node with the capacitorinsulating film therebetween.

According to a second aspect of the invention, a semiconductor memorydevice includes a semiconductor substrate and a storage node provided onthe semiconductor substrate. The storage node is provided at its outersurface with a concave portion hollowed inwardly from the outer surface.The semiconductor memory device further includes a capacitor insulatingfilm which covers the whole outer surface of the storage node includinga surface of the concave portion. There is also provided a cell platecovering the outer surface of the storage node with the capacitorinsulating film therebetween.

A third aspect of the invention provides a method of manufacturing asemiconductor memory device which includes a plurality of cylindricalcapacitors adjoining each other. In the method, a word line is firstformed on a semiconductor substrate. Source/drain regions are formed ona main surface of the semiconductor substrate with the word line betweeneach other. A bit line connected to one of the source/drain regions isformed on the semiconductor substrate. A cylindrical storage node isformed on the semiconductor substrate. The cylindrical storage nodeincludes a bottom conductive portion, which is connected to the other ofthe source/drain regions and spreads up to a position above the wordline with the insulating layer therebetween, and a side wall conductiveportion, which is continuously extends upwardly from an outer peripheryof the bottom conductive portion and has inner and outer walls.Protruded conductors are selectively formed only on the bottomconductive portion and the inner wall of the side wall conductiveportion of the cylindrical storage node. A capacitor insulating film isformed to cover the whole outer surface of the cylindrical storage nodeincluding outer surfaces of the protruded conductors. A cell plate isformed to cover the outer surface of the cylindrical storage node withthe capacitor insulating film therebetween.

A fourth aspect of the invention provides a method of manufacturing asemiconductor memory device which includes a plurality of cylindricalcapacitors adjoining each other. In the method, a word line is formed ona semiconductor substrate. Source/drain regions are formed on a mainsurface of the semiconductor substrate with the word line between eachother. A bit line connected to one of the source/drain regions is formedon the semiconductor substrate. A first conductive film, which isconnected to the other of the source/drain regions and covers the wordline and the bit line, is formed on the whole upper surface of thesemiconductor substrate with an insulating layer therebetween. A patternof an insulating member, which extends upwardly and has an upper endsurface and a side wall, is formed at a region on the first conductivefilm except for a region on which the cylindrical capacitor is formed. Asecond conductive film is formed on the whole upper surface of the firstconductive film to cover the upper end surface and the side wall of thepattern of the insulating member. Protruded conductors are formed on thewhole surface of the second conductive film. A portion of the secondconductive film located above the upper end surface of the pattern ofthe insulating member is selectively removed by etching to expose theupper end surface of the insulating member. A portion of the pattern ofthe insulating member starting from the exposed upper end surface isremoved by etching to form a cylindrical storage node, which includes abottom conductive portion bearing the protruded conductors, and a sidewall conductive portion continuously extending upwardly from an outerperiphery of the bottom conductive portion and being provided at itsinner wall with the protruded conductors. A capacitor insulating film isformed to cover a whole outer surface of the cylindrical storage nodeincluding surfaces of the protruded conductors. A cell plate is formedto cover the outer surface of the cylindrical storage node with thecapacitor insulating film therebetween.

A fifth aspect of the invention provides a method of manufacturing asemiconductor memory device in which a storage node made of silicon isfirst formed on a semiconductor substrate. A metal film is formed tocover a surface of the storage node. The storage node covered with themetal film is heated to form a silicide film on the surface of thestorage node. The silicide film is condensed. The condensed silicidefilm is removed from the surface of the storage node. A capacitorinsulating film is formed to cover the surface of the storage node. Acell plate is formed to cover the outer surface of the storage node withthe capacitor insulating film therebetween.

According to the semiconductor memory device having the cylindricalcapacitor of the first aspect of the invention, since the cylindricalstorage node is provided at its inner wall with the protruded conductorswhich increases a surface area, a capacitor capacity is increased. Sincethe protruded conductor is not provided at an outer wall of thecylindrical storage node, short-circuit between the adjoining storagenodes is prevented.

Since the protruded conductor is not provided at the outer wall of thecylindrical storage node, the cell plate covers well the surface of thestorage node.

According to the semiconductor memory device of the second aspect of theinvention, the storage node is provided at its outer surface withconcave portions hollowed inwardly from the outer surface, so that anarea of the outer surface of the storage node increases, and thus acapacitor capacity increases.

The methods of manufacturing the semiconductor memory device accordingto the third and fourth aspects, since the protruded conductors areformed at only the inner wall of the cylindrical storage node, thesemiconductor memory device can prevents short-circuit between thecylindrical storage node and an adjacent cylindrical storage nodeadjoining to the same, and has a large capacitor capacity.

According to the method of manufacturing the semiconductor memory deviceof the fifth aspect of the invention, the storage node covered with themetal film is heated to from the silicide film on the surface of thestorage node. Thereafter, the silicide film is condensed, and then, thecondensed silicide film is removed from the surface of the storage node.Thereby, the concave portions hollowed inwardly from the surface of thestorage node are formed at the surface of the storage node, so that thestorage node has a large surface area.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional DRAM;

FIG. 2 is an equivalent circuit diagram of memory cells in theconventional DRAM;

FIG. 3 is a cross section of a conventional DRAM memory cell with astacked type capacitor;

FIG. 4 is a plan of a memory array in an art relevant to the invention;

FIG. 5 is a cross section taken along line V--V in FIG. 4;

FIGS. 6-20 are fragmentary cross sections of the semiconductor memorydevice at 1st-21st steps in a process of manufacturing the semiconductormemory device shown in FIG. 5, respectively;

FIG. 21 is a cross section of a semiconductor memory device in anotherart relevant to the invention;

FIG. 22 is a fragmentary cross section of the semiconductor memorydevice at a major step in a process of manufacturing the semiconductormemory device shown in FIG. 21;

FIG. 23 is a fragmentary cross section of the semiconductor memorydevice for pointing out a problem in the process of manufacturing thesemiconductor memory device shown in FIG. 21;

FIG. 24 is a cross section of a semiconductor memory device of anembodiment of the invention taken along a line parallel to a bit line;

FIG. 25 is a cross section of the semiconductor memory device of theembodiment of the invention taken along a line parallel to a word line;

FIGS. 26A and 26B show distinctive features of the semiconductor memorydevice of the embodiment of the invention;

FIGS. 27-54 are fragmentary cross sections of the semiconductor memorydevice of the first embodiment of the invention at 1st to 28th steps ina process of manufacturing the semiconductor memory device,respectively;

FIGS. 55-68 are fragmentary cross sections of a semiconductor memorydevice of a second embodiment of the invention at 1st to 14th steps in aprocess of manufacturing the semiconductor memory device, respectively;

FIGS. 69A, 69B, 69C and 69D are cross sections showing a basic conceptof a method of manufacturing a semiconductor memory device according toa third embodiment of the invention;

FIGS. 70-74 are fragmentary cross sections of a semiconductor memorydevice of the third embodiment of the invention at 1st to 5th steps in aprocess of manufacturing the semiconductor memory device, respectively;

FIG. 75 is a cross section of a major portion of a semiconductor memorydevice according to a fourth embodiment of the invention;

FIG. 76 is a cross section of a major portion of a semiconductor memorydevice according to a fifth embodiment of the invention; and

FIG. 77 is a cross section of a major portion of a semiconductor memorydevice according to a sixth embodiment of the invention.

FIG. 78 is a cross section of a semiconductor memory device of theseventh embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the invention will be described below with reference tothe drawings.

FIG. 24 is a cross section of a semiconductor memory device of anembodiment of the invention taken along line parallel to a bit line.FIG. 25 is a cross section of the semiconductor memory device of theembodiment of the invention taken along line parallel to a word line.The semiconductor memory device of the embodiment of the invention canbe represented by the same plan as FIG. 4.

The semiconductor memory device of the embodiment is similar to theconventional semiconductor memory device shown in FIG. 5 except forpoints described below. The same or corresponding portions bear the samereference numbers and will not be described later.

The semiconductor memory device of the invention has a distinctivefeature that the cylindrical storage node 26 formed of the bottomconductive portion 27 and side wall conductive portion 28 is provided atits inner wall with silicon particles 41 which are protruded conductorsof hemispheric shape and are projected in a radially inward direction ofthe cylindrical shape of the storage node 26. There is provided thecapacitor insulating film 29 which covers the whole outer surface of thecylindrical storage node 26 including the outer surfaces of the siliconparticles 41. See FIG. 25.

The capacitor capacity of the semiconductor memory device having theabove structure will be described below.

Referring to FIG. 26A and 26B represent a cross section and a plan ofthe storage node, it is assumed that the side wall conductive portion 28has a height of 6000 Å and the storage node has the sizes (representedby l×m in FIG. 26B) of 1.0×0.4 μm, and that the capacitor insulatingfilm has a thickness of 40 Å in terms of SiO2. In this case, aconventional device including no silicon particle has a capacitorcapacity of 22 fF. Meanwhile, a capacitor capacity of 27 fF can beobtained in the embodiment in which the silicon particles are ofhemispherical form as readily seen from their semi-circularcross-sections in FIGS. 24 and 25 and are formed on the inner wall ofthe cylindrical storage node to obtain the surface area of the capacitorcapacity which is 1.5 times as large as that of the conventionalcapacitor. If the surface area of the capacitor is twice as large asthat of the conventional device, the capacitor capacity of 33 fF isobtained. It should be noted that the capacitor capacity of 25 fF isrequired for ensuring the device characteristics.

Then, a method of manufacturing the semiconductor memory device shown inFIG. 24 will be described below.

Embodiment 1

FIGS. 27-54 are fragmentary cross sections of the semiconductor memorydevice at respective steps in the process of manufacturing thesemiconductor memory device provided with cylindrical capacitors shownin FIG. 24.

Referring to FIG. 27, the field oxide film 13 is formed at the mainsurface of the silicon substrate 10. The gate oxide film 34 is formed onthe surface of the silicon substrate 10. The word line film 12 andinterlayer insulating film 24 are successively formed on the gate oxidefilm 34.

Referring to FIG. 28, the word line film 12 and interlayer insulatingfilm 24 are selectively etched by photolithography to form a pluralityof word lines 12a, 12b, 12c and 12d. At this step, the interlayerinsulating films 24 are remained on each of the word lines 12a, 12b, 12cand 12d.

Referring to FIG. 29, an insulating film 42 is formed on the siliconsubstrate 10 to cover the word lines 12a, 12b, 12c and 12d.

Referring to FIGS. 29 and 30, anisotropic etching is effected to etchthe insulating film 42 for forming side wall spacers on the side wallsof the word lines 12a, 12b, 12c and 12d. Thereby, the word lines 12a,12b, 12c and 12d are covered with first insulating films 43a, 43b, 43cand 43d. Using the first insulating films 43a, 43b, 43c and 43d as amask, impurity ions are implanted into the main surface of the siliconsubstrate 10, whereby the source/drain regions 11 are formed at the mainsurface of the silicon substrate 10.

Referring to FIG. 31, an insulating film 44 is formed to cover the wordlines 12a, 12b, 12c and 12d which are covered with the first insulatingfilms 43a, 43b, 43c and 43d. The insulating film 44 is selectivelyetched to form the bit line contact hole 18. A bit line film and aninsulating film (TEOS oxide film), which are in contact with thesource/drain region 11 through the bit line contact hole 18, aresequentially formed on the silicon substrate 10. These bit line film andinsulating film are selectively patterned to from the bit line 17. Atthis step, the insulating film 35 is remained on the bit line 17.

Referring to FIG. 32, an insulating film 45 is formed on the siliconsubstrate 10 to cover the bit line 17 provided with the insulating film35.

Referring to FIG. 33, the insulating film 45 is etched back to form sidewall spacers on the side walls of the bit line 17 and expose partiallythe source/drain regions 11.

Referring to FIG. 34, the whole surface of the silicon substrate 10 iscovered with a silicon nitride film 46.

Referring to FIGS. 35 and 36, using the resist pattern 38 as a mask, thesilicon nitride film 46 is selectively etched to form the contact hole25 for exposing the surface of the other source/drain region 11. Then,the resist pattern 38 is removed.

Referring to FIG. 37, a first silicon layer 47 containing phosphorus orthe like added thereto is formed on the whole upper surface of thesilicon substrate 10. The first silicon layer 47 is connected to theother source/drain region 11 and covers the bit line 17 and word lines12a, 12b, 12c and 12d with insulating layers therebetween. The firstsilicon layer 47 is preferably amorphous.

Referring to FIG. 38, an insulating film 48 made of a TEOS oxide film isformed on the first silicon layer 47. Formation of the insulating film48 is preferably carried out at a relatively low temperature lower thanabout 500° C. so that the first silicon layer 47 may not change fromamorphous to polysilicon.

Referring to FIG. 39, resist patterns 49 having a predeterminedconfiguration are formed on the insulating layer 48. A width w of theresist pattern 49 determines a distance between adjoining capacitors.

Referring to FIGS. 39 and 40, the insulating layer 48 is selectivelyetched, using the resist patterns 49 as a mask. Referring to FIGS. 40and 41, the resist pattern 49 is removed.

Referring to FIGS. 41 and 42, a second silicon layer 50 containingimpurity such as phosphorus introduced thereinto is deposited by the CVDmethod on the whole upper surface of the first silicon layer 47 so thatthe second silicon layer 50 covers an upper end surface 48a and a sidewall 48b of each insulating layer 48. The second silicon layer 50 ispreferably amorphous.

Referring to FIG. 43, resist 51 is applied to the surface of the siliconsubstrate 10 so that it completely covers an uppermost surface 50a ofthe second silicon layer 50.

Referring to FIGS. 43 and 44, the resist 51 is etched back to expose theuppermost surface 50a of the second silicon layer 50.

Referring to FIGS. 44 and 45, the exposed uppermost surface 50a of thesecond silicon layer 50 is removed by etching.

Referring to FIGS. 45 and 46, the insulating layer 48 is removed byetching with HF liquid or the like.

Referring to FIGS. 46 and 47, anisotropic etching is effected to removethe exposed portion 47a of the first silicon layer 47 in a self-aligningmanner. In this processing, the silicon nitride film 46 functions as anetching stopper to prevent further etching.

By etching and removing the exposed portion 47a of the first siliconlayer 47, the basic configuration of the cylindrical storage node 26 iscompleted, in which the bottom conductive portion 27 is connected to theother source/drain region 11 and spreads up to an area over the wordlines 12a, 12b, 12c and 12d with the insulating layers therebetween, andthe side wall conductive portion 28 continuously and upwardly extendsfrom the outer periphery of the bottom conductive portion 27 and has theinner and outer walls 28a and 28b.

Referring to FIGS. 47 and 48, the cylindrical storage node 26 and eachof cylindrical storage nodes 261 and 262 adjoining to the cylindricalstorage node 26 define a space 260 between them, which is filled with aninsulating film 52 in a liquid state such as spin-on glass. Filling withthe insulating film 52 is carried out by etch back of a spin-on glassfilm applied to the whole surface of the silicon substrate 10.

Referring to FIGS. 48 and 49, the resists 51 filling the storage nodes26, 261 and 262 are removed by etching with O₂ plasma.

Referring to FIGS. 49 and 50, the silicon substrate 10 is rinsed offwith acid and alkali, and then, the silicon substrate 10 is placed in aCVD chamber (not shown). The pressure-reduced CVD chamber is set to atemperature of 600° C. and a high vacuum condition of not more than×10-7 Torr. Thereafter, Si₂ H₆ gas is introduced into thepressure-reduced CVD chamber for 10 to 20 seconds. Thereby, minutesilicon particles 41, i.e., protruded conductors are formed on the innerwalls of the cylindrical storage nodes 26, 261 and 262. The siliconparticle 41 has a hemispherical shape with a diameter of about 100 Å.The silicon particles 41 are formed by the following mechanism. First,thin films of silicon are formed on the inner walls of the cylindricalstorage nodes 26, 261 and 262, and then, owing to rise of thetemperature, silicon cores gather to form the minute silicon particles41. Formation of the silicon particles 41 is promoted if the firstsilicon layer 47 is amorphous.

Referring to FIGS. 50 and 51, the insulating film 52 is removed with HFliquid. In this processing, the insulating layer 35 is not etched owingto existence of the silicon nitride film 46.

Referring to FIGS. 51 and 52, the capacitor insulating film 29 which isa high dielectric film made of compound containing silicon nitride,silicon oxide, tantalum pentaoxide, hafnium oxide, BaSrTiO₂, PbZnTiO orSrTiO is formed on the outer surfaces of the cylindrical storage nodes26, 261 and 262.

Referring to FIG. 53, the cell plate 30 is formed on the siliconsubstrate 10 to cover the outer surfaces of the cylindrical storagenodes 26, 261 and 262 with the capacitor insulating film 29therebetween. The cell plate 30 may be made of polysilicon into whichimpurity is introduced.

Referring to FIG. 54, the interlayer insulating film 31 is formed on thewhole surface of the silicon substrate 10 to cover the cell plate 30.The interconnection layers 32 having predetermined configurations areformed on the interlayer insulating film 31. The protection film 33 isformed on the whole surface of the silicon substrate 10 to cover theinterconnection layers 32.

The semiconductor memory device having the cylindrical capacitors whichis manufactured as described above can ensure a sufficient capacitorcapacity with a small occupied area.

Embodiment 2

This embodiment relates to another method of forming the protrudedconductors on the inner wall of the cylindrical storage node.

Although not shown, the same steps as those shown in FIGS. 27-33 arefirst carried out similarly to the embodiment 1.

Referring to FIG. 55, the insulating layer 48 is formed on the firstsilicon layer 47.

Referring to FIG. 56, resist patterns 49 having a predeterminedconfiguration is formed on the surface of the insulating layer 48. Thewidth w of each resist pattern 49 determines a distance betweenadjoining capacitors.

Referring to FIGS. 56 and 57, the insulating layer 48 is selectivelyetched using the resist patterns 49 as a mask.

Referring to FIGS. 57 and 58, the resist patterns 49 are removed, andthen the second silicon layer 50 containing impurity such as phosphorusintroduced thereinto is deposited on the whole surface of the siliconsubstrate 10 by the CVD method to cover the upper end surface and sidewall of each insulating layer 48 The silicon substrate is placed in thepressure-reduced CVD chamber. The pressure-reduced CVD chamber is set toa temperature of 600° C. and a high vacuum condition of not more than1×10-7 Torr. Si₂ H₆ gas is introduced into the pressure-reduced CVDchamber for 10 to 20 seconds, whereby the silicon particles 41 areformed on the whole surface of the second silicon layer 50 as shown inFIG. 59.

Referring to FIG. 60, the resist 51 is applied to the surface of thesilicon substrate 10 so that it completely covers the uppermost surface50a of the second silicon layer 50.

Referring to FIGS. 60 and 61, the resist 51 is etched back to expose theuppermost surface 50a of the second silicon layer 50.

Referring to FIGS. 61 and 62, the uppermost surface 50a of the secondsilicon layer 50 is etched and removed to expose the upper end surfaceof each insulating layer 48.

Referring to FIGS. 62 and 63, the insulating layer 48 is removed byeffecting etching on its exposed portion with HF liquid or the like.

Referring to FIGS. 63 and 64, by etching the exposed portion 47a of thefirst silicon layer 47, the basic configuration of the cylindricalstorage node 26 is completed, in which the bottom conductive portion 27is provided at its inner wall with the silicon particles 41, and theside wall conductive portion 28 continuously and upwardly extends fromthe outer periphery of the bottom conductive portion 27 and is providedat its inner wall with the silicon particles 41.

Referring to FIGS. 64 and 65, the resist 51 is removed.

Referring to FIGS. 65 and 66, the capacitor insulating film 29 is formedon the whole surface of the silicon substrate 10 to cover the outersurface of the cylindrical storage node 26 including the surfaces of thesilicon particles 41.

Referring to FIGS. 66 and 67, the cell plate 30 is formed over the outersurface of the cylindrical storage node 26 with the insulating film 29therebetween. The interlayer insulating film 31 is formed on the siliconsubstrate 10 to cover the cell plate 30.

Referring to FIGS. 67 and 68, the interconnection layers 32 are formedon the interlayer insulating film 31. The protection film 33 is formedon the interlayer insulating film 31 to cover the interconnection layers32.

Embodiment 3

FIGS. 69A, 69B, 69C and 69D show a basic concept of a method ofmanufacturing the semiconductor memory device according to thisembodiment. Referring to FIG. 69A, a metal film, i.e., Ti film 90 ofabout 500 to 1000 Å in thickness is deposited by the sputter method onthe storage node 26 made of silicon.

Referring to FIGS. 69A and 69B, the storage node 26 covered with the Tifilm 90 is heated in insert gas such as Ar at a temperature of 800° to900° C. for more than 30 seconds to change the Ti film 90 into asilicide film 92 (TiSi2). In the case of Ti, the silicide film 92 hasthe uniform thickness as shown at FIG. 69B when treated at a temperaturenot lower than 700° C.

However, treatment at a high temperature higher than 800° C. promotescondensing reaction of the silicide film 92 as shown at FIG. 69C. Thiscondensing reaction is similar to a phenomenon in which a water dropletchanges into a spherical form on a glass plate to minimize its surfacearea, and is a phenomenon in which atoms move to minimize the surfaceenergy of TiSi2 itself and which becomes remarkable as the temperaturerises.

Referring to FIG. 69D, the condensed TiSi2 films 92 are removed with HFliquid or the like to leave hemisphere-shaped portions 93 at the surfaceof the silicon substrate. Thereafter, the capacitor insulating film isformed on the surface of the silicon storage node 26, whereby thecapacitor having a large surface area is obtained.

Although Ti has been described as an example of component of the metalfilm, Ta, Hf and Zr may be preferable.

FIGS. 70-74 are cross sections showing a method of manufacturing thesemiconductor memory device including the cylindrical capacitor to whichthe aforementioned basic concept is applied.

First, steps shown in FIGS. 27-47 are carried out.

Thereafter, the resist 51 is removed as can be seen from FIGS. 47 and70.

Referring to FIG. 71, the Ti film 90 is deposited on the whole surfaceof the cylindrical storage node 26 by the sputter method.

Referring to FIGS. 71 and 72, the cylindrical storage node 26 coveredwith the Ti film 90 is thermally processed in Ar at a temperature of900° C. for 60 minutes by the lamp anneal method. Owing to this heattreatment, the Ti film 90 changes into the silicide film 92 and furtherchanges into the condensed forms as shown in the figure.

Referring to FIGS. 72 and 73, the silicide films 92 are removed byetching in solution containing HF. Although the TiSi2 dissolves in HF,Si does not substantially dissolve in HF. By removing the silicide films92, the storage node 26 has the surface which is complementary in shapeto the TiSi2/Si interface and has the hemispherical concave portions 93hollowed inwardly from the outer surface. During the processing with theHF solution, the insulating film 35 formed of the TEOS oxide film is notetched because it is protected by the SiN film 46.

In this embodiment, metal such as Ti may contaminate the storage node26. However, the oxide of metal such as Ti has a high dielectricconstant, and the use of the same as a capacitor insulating film hasbeen studied. Therefore, no problem is caused even if metal such as Tiand Ta remains in Si of the storage node 26.

Referring to FIG. 74, the outer surface of the cylindrical storage node26 is covered with the capacitor insulating film 29. The cell plate 30is formed on the silicon substrate 10 to cover the outer surface of thecylindrical storage node 26 with the capacitor insulating film 29therebetween. The interlayer insulating film 31 is formed on the surfaceof the silicon substrate 10 to cover the cell plate 30. Theinterconnection layers 32 having a predetermined configuration areformed on the interlayer insulating film 31. The protection film 33 isformed on the whole surface of the silicon substrate 10 to cover theinterconnection layers 32.

The semiconductor memory device having the cylindrical capacitors whichis manufactured as described above can sufficiently ensure the capacitorcapacity with a small occupied area.

Embodiment 4

In the aforementioned embodiment, it has been described, as an example,that the silicide films 92 are removed after condensing them as shown inFIGS. 72 and 73. In this embodiment 4, as shown in FIG. 75, thecapacitor insulating film 29 is deposited on the whole surface of thestorage node 26 without removing the silicide films 92. In thisembodiment, the storage node 26 is provided with hemispherical outwardconvex portions 92. Also in this embodiment, the storage node 26 canhave the outer surface of a large area, and thus can sufficiently ensurethe capacitor capacity.

Embodiment 5

The embodiments which have been described have the storage nodes of thecylindrical form as shown in FIG. 74. The present invention, however, isnot restricted to them, and may be applied to a structure includingstacked capacitors as shown in FIG. 76.

Embodiment 6

FIG. 77 is a fragmentary cross section of a semiconductor memory deviceof an embodiment 6. In this embodiment, the concept of the inventionshown in FIG. 75 is applied to the conventional stacked type capacitor.Also in this embodiment, a sufficiently large capacitor capacity can beensured with a small occupied area.

Embodiment 7

At the surface of a semiconductor substrate 200, an isolating oxide film201 is formed. On semiconductor substrate 200, a gate electrode 202 isprovided. In semiconductor substrate 200 on both sides of gate electrode202, source/drain layers 203, 203 are provided. In semiconductorsubstrate 200, a trench 204 for forming a capacitor is provided. Animpurity diffused layer 205 which will be a storage node is providedsurrounding trench 204. One of source/drain layers 203 is connected toimpurity diffused layer 205. On the inner wall surface of trench 204,silicon particles 206 are formed. A capacitor insulating film 207 coversthe inner wall surface of the trench 204, so as to cover siliconparticles 206. A cell plate 208 is filled in trench 204.

Bit line 209 is connected to the other one of source/drain layers 203.In the semiconductor memory device of Embodiment 7, since surface areaof the storage node is enlarged by means of silicon particles 206,capacitor capacitance can be increased by the increase of the surfacearea.

The silicon particles 206 are formed in the following manner. Namely, anamorphus thin film is formed on the inner wall surface of trench 204.Thereafter, by effecting thermal treatment, silicon particles 206 areformed on the inner wall surface of the trench 204.

According to the semiconductor memory device of the first aspect of theinvention, as described hereinbefore, the cylindrical storage node isprovided at its inner wall with the protruded conductors, so that thecapacitor capacity is increased owing to the large surface area of theprotruded conductors. Short-circuit does not occur between thecylindrical storage node and an adjacent cylindrical storage node.

According to the semiconductor memory device of the second aspect of theinvention, the storage node is provided at its outer surface withconcave portions hollowed inwardly from the outer surface, so that theouter surface of the storage node has a large area, resulting in a largecapacitor capacity.

According to the method of manufacturing the semiconductor memory deviceof the third and fourth aspects of the invention, the protrudedconductors are formed only at the inner wall of the cylindrical storagenode, so that short-circuit does not occur between the cylindricalstorage node and an adjacent cylindrical storage node adjoining to theformer storage node., and the semiconductor memory device can have alarge capacitor capacity.

According to the method of manufacturing the semiconductor memory deviceof the fifth aspect of the invention, the storage node covered with themetal film is heated to form the silicide film on the surface of thestorage node. Thereafter, the silicide film is condensed, and then thecondensed silicide films are removed from the surface of the storagenode. Thereby, the concave portions hollowed inwardly from the surfaceof the storage node are formed at the surface of the storage node, sothat the storage node has a large surface area.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor memory device, comprising:a semiconductor substrate which is provided at a main surface with a conductive layer; a word line and a bit line formed on said semiconductor substrate; an insulating film provided on said semiconductor substrate and covering said word line and said bit line; a contact hole provided in said insulating film for partially exposing said conductive layer; a cylindrical storage node electrically connected to said conductive layer; wherein said cylindrical storage node includes a first bottom conductive layer which is in contact with said conductive layer through said contact hole and is disposed along a surface of said insulating film, a second bottom conductive layer provided on said first bottom conductive layer, a side wall conductive portion, which is continuous with and extends upwardly from an outer periphery of said second bottom conductive layer and has an inner wall and an outer wall, and a protruded conductor, which is provided at said inner wall of said cylindrical storage node formed of said second bottom conductive layer and said side wall conductive portion and protrudes in a radially inward direction of said cylindrical storage node, said protruded conductor comprising a plurality of protrusions which are in the shape of hemispheres each connected at the base thereof to the inner wall of said cylindrical storage node, wherein said protruded conductor is not provided at said outer wall of said cylindrical storage node; a capacitor insulating film which covers the entire outer surface of said cylindrical storage node including outer surfaces of said hemispherically shaped protrusions of said protruded conductor; and a cell plate covering said outer surface of said cylindrical storage node with said capacitor insulating film therebetween.
 2. A semiconductor memory device, comprising:a semiconductor substrate; a storage node comprising polysilicon provided on said semiconductor substrate, said storage node being provided at an outer surface with a concave portion hollowed inwardly from said outer surface, said concave portion comprising a plurality of concave hemispherical surfaces with their bases at said outer surface of said storage node, with a metal contaminant selected from the group consisting of Ti, Ta, Hf, and Zr remaining in said storage node as a result of processing to form said concave hemispherical surfaces; a capacitor insulating film which covers the entire outer surface of said storage node including a surface of said concave portion and the concave hemispherical surfaces thereat; and a cell plate covering said outer surface of said storage node with said capacitor insulating film therebetween.
 3. The semiconductor memory device according to claim 2, wherein:said concave portion is hemispherical in shape.
 4. The semiconductor memory device according to claim 2, further comprising:a silicide film which is disposed between said storage node and said capacitor insulating film for filling said concave portion.
 5. The semiconductor memory device according to claim 2, wherein:said storage node includes an upwardly extending cylindrical storage node. 